Referierte Artikel in wissenschaftlichen Fachzeitschriften
Kässens, J. Ch., Wienbrandt, L., González-Dominguez, J., Schmidt, B., Schimmler, M.:
High-Speed Exhaustive 3-locus Interaction Epistatis Analysis on FPGAs
Journal of Computational Science, Vol. 9, pp 131-136, 2015
González-Dominguez, J., Wienbrandt, L., Kässens, J. Ch., Ellinghaus, D., Schimmler, M., Schmidt, B.:
Parallelizing Epistatis Detection in GWAS on FPGA and GPU-accelerated Computing Systems,
IEEE/ACM Transactions on Computational Biology and Bioinforamtics, 12 (5), 2015, pp.982-994
Wittig, M., Anmarkrud, J., Kässen, J., Koch, S., Forster, M., Ellinghaus, E., Hov Roksund, J., Sauer, S., Schimmler, M.,
Ziemann, M., Görg,S., Jacob, F., Karlsen, T., Franke, A.:
Development of a high resolution NGS-based HLA-yping and analysis pipeline,
Nicleic Acids Research, 43 (11):e70, 2015
Wienbrandt, L., Kässens, J. Ch., González-Dominguez, J., Schmidt, B.,
Ellinghaus, D., Schimmler, M.:
FPGA-based accelaration of detecting statistical epistatis in GWAS,
Procedia Computer Science, Vol. 29 (2014), pp. 220-230
Starke, Ch., Grossmann, V., Wienbrandt, L., Koschnicke, S., Carstens, J., Schimmler, M.:
Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA,
International Journal of Reconfigurable Computing, 2012
Schimmler, M., Wienbrandt, L., Güneysu, T., Bissel, J.:
Book Chapter in 'Bioinformatics: High Performance Parallel Computer Architectures',
edited by Bertil Schmidt, CRC Press, 2010
Toledo Munioz, M.B., Spors, K., Bracht, W., Schimmler, M.:
Agentenbasierte Modellierung und Analyse von Verbindungen im Produktentstehungsprozess,
Zeitschrift für wirtschaftliche Fabrikplanung (ZWF), 100, 319-323, 2005
Schimmler, M., Schmidt, B., Lang, H.-W.:
A Bit-Serial Floating-Point Unit for a massively parallel system on a chip,
Journal of Parallel Algorithms and Applications, forthcoming, 2004
Schimmler, M., Schmidt, B., Lang, H.-W., Heithecker, S.:
An area-efficient bit-serial integer and GF (2n) multiplier,
Microelectronic Engineering 84 , pp 253-259, 2004
Schmidt, B., Schimmler, M., Schröder, H.:
A Massively Parallel Architecture for Public-Key Cryptography,
International Journal of Computer Research, forthcoming, 2004
Schmidt, B., Schimmler, M., Schröder, H.:
A Hybrid Architecture for Bioinformatics,
International Journal on Future Generation Computer Systems 18, pp 855-862, 2002
Schmidt, B., Schimmler, M., Schröder, H.:
Tomographic Image Reconstruction on the Instruction Systolic Array
Computing and Informatics, Vol. 20, No. 1, pp 27-42, 2001
Schmidt, B., Schimmler, M., Schröder, H.:
A Morphological Approach to Hough Transform on an Instruction Systolic Array,
Computers and Artificial Intelligence, Vol. 18, No. 6, pp 541-557, 1999
Schimmler, M.:
Parallel Strong Orientation on a Mesh-Connected Computer,
Parallel Computing, Vol. 14, pp 301-308, 1991
Krishnamurty, E.V., Kunde, M., Schimmler, M., Schröder, H.:
Systolic Algorithm for Tensor Products of Matrices: Implementation and Applications,
Parallel Computing, Vol 13, pp 301-308, 1990
Schimmler, M., Starke, C.:
A Correction Network for N-Sorters,
SIAM Jounal on Computations, pp 1179-1187, 1989
Schimmler, M., Schröder, H.:
A Simple Systolic Method to Find all Bridges on an Undirected Graph,
Parallel Computing, Vol 12, pp 107-111, 1989
Schimmler, M., Starke, C.:
Design of a Fault Tolerant Sorting Chip,
NORCHIP News, Vol 6, No 7, pp 3-5, 1989
Kunde, M., Lang, H.W., Schimmler, M., Schmeck, H., Schröder, H.:
The Instruction Systolic Array and its Relation to other Models of Parallel Computers,
Parallel Computing, Vol 7, pp 25-39, 1988
Lang, H.W., Schimmler, M., Schmeck, H., Schröder, H.:
Systolic Sorting on a Mesh-Connected Network,
IEEE Transactions on Computers, C-34, pp 652-658, pp 652-658, 1985
Referierte Artikel in technischen Fachzeitschriften
Schatz, F., Koschnicke, S., Paulsen,N., Schimmler M.
Master/Slave Assignment Optimization for High Performance Computing in an EC2 Cloud Using MPI
Network Protocols and Algorithms, ISSN 1943-3581
Volume 4, 2012, No. 1, Pages 22-33
Macrothink Instiute, 2012
M. B. Toledo Munioz, K. Spors, W. Bracht, M. Schimmler:
Agentenbasierte Modellierung und Analyse von Verbindungen im Produktentstehungsprozess
Zeitschrift für wirtschaftliche Fabrikplanung (ZWF), 100, 319-323, 2005
Schimmler, M.:
Feinkörnige Parallelrechner,
Carolo Wilhelmina Mitteilungen, Schwerpunktheft Informatik, 1999
Schimmler, M.:
Nachbrenner: Parallel rechnen über eine PC-Zusatzkarte,
Elektronik Praxis No. 3, pp 110-114, 1996
Bertuch, M, Schimmler, M.:
3000 Mips im PC,
c't Oktober 95, p 106, 1995
Referierte Veröffentlichungen auf internationalen Konferenzen
Koschnicke, S., Grossmann, V., Starke, Ch., Schimmler, M.:
Quality and Consistency Assurance of Quote Data for Algorithmic Trading Strategies,
IEEE Computational Intelligence for Financial Engineering und Economics, London, 2014
Abbas, A., Voß, R., Wienbrandt, L., Schimmler, M.:
An Efficient Implementation of PBKDF2 with RIPEMD-160 on Multiple FPGAs,
2014 IEEE 20th International Conference on Parallel and Distributed Systems (ICPADS), pp. 454-461, Dec. 2014
Wienbrandt, L., Siebert, D., Schimmler, M.:
Improvement of BLASTp on the FPGA-Based High-Performance Computer RIVYERA,
ISBRA 2012, Dallas, USA
Schatz, F., Wienbrandt, L., Schimmler, M.:
Probability Model for Boundaries of Short-Read Sequencing
ACC 2012, Kochi, Indien
Starke, Ch., Grossmann, V., Wienbrandt, L., Schimmler, M.:
An FPGA-Implementation of an Investment Strategy Processor
ICCS 2012, Omaha, USA
Abbas, A., Rathje, C. A., Wienbrandt, L., Schimmler, M.:
Dictionary Attack on TrueCrypt with RIVYERA S3-5000
ICPADS 2012, Singapur
Schatz, F., Koschnicke, S., Paulsen, N., Starke, Ch., Schimmler, M.:
MPI Performance Analysis of Amazon EC2 Cloud Services for High Performance Computing
Advances in Computing and Communications,
Volume 190 of Communications in Computer and Information Science,
pages 371-381, Springer Berlin Heidelberg, 2011
Wienbrandt,L., Baumgart S., Bissel J., Schatz F., Schimmler M.:
Massively parallel FPGA-based implementation of BLASTp with the two-hit method
Procedia Computer Science
Volume 4, 2011, Pages 1967-1976
Proceedings of the International Conference on Computational Science, ICCS 2011
Schatz, F., Möller, S., Schimmler, M.:
Smarti - A fast short read alignment algorithm
Research in Computational Molecular Biology
15th Annual International Conference, RECOMB, Vancouver, Kanada, 2011
Wienbrandt, L., Baumgart, S., Bissel, J., Yeo, C., Schimmler, M.:
Using the Reconfigurable Massively Parallel Architecture COPACOBANA 5000 for
Applications in Bio-Informatics, ICCS 2010, Procedia ComputerScience,
Elsevier, 1-8, 2010
Wienbrandt, L., Schimmler, M.,:
Collecting Statistical Information in DNA Sequences for the Detection of Motifs
Proc. BIOCOMP 2010, 274-278, 2010
Schatz, F., Schimmler, M.:
Boundaries for short-read, low coverage denovo assembly and resequencing
9th European Conference on Computational Biology, ECCB10, Gent, Belgium, 2010
Schatz, F., Schimmler, M.:
A priori estimation of contig length distribution of short-read sequencing.
Research in Computational Molecular Biology
14th Annual International Conference, RECOMB, Lisbon, Portugal, 2010
Güneysu, T., Pfeiffer, G., Paar, C., Schimmler, M.:
3 Years of Evolution: Cryptanalysis with COPACOBANA, Special-purpose Hardware for Attacking Cryptographic Systems
SHARCS Lausanne, Switzerland, 2009
Bunimov, V., Schimmler, M.:
An Efficient Algorithm for Scalable Modular Multiplication on Standard Processors,
Proc. 3 rd. International Conference on Information Security and Privacy (ISP),
July 13-16, Orlando, USA 2009
Pfeiffer G., Baumgart, S., Schröder, J., Schimmler, M.:
A Massively Parallel Architecture for Bioinformatics
ICCS 2009, International Conference on Computational Science
9th International Conference Baton Rouge, LA, USA, May 25-27, 2009
Schröder, J., Wienbrandt, L., Pfeiffer, G., Schimmler, M.:
Massively Parallelized DNA Motif Search on the Reconfigurable Hardware Platform PRIB, Melbourne, 2008
Schröder, J., Schimmler, M., Schröder, H., Tischer, K.:
BMA - Boolean Matrices as Model for Motif Kernels
International Conference on Bioinformatics, Computational Biololy, Genomics and
Chemoinformatics (BCBGC-08), Orlando, USA, 2008
Güneysu, T., Paar, C., Pfeiffer, G., Schimmler, M.:
Enhancing COPACOBANA for Advanced Applications in Cryptography and Cryptoanalysis
Proc. International Conference on Field Programmable Logic and Applications FPL, Heidelberg, pp.675-678, 2008
Pfeiffer, G., Schimmler, M.:
Optimizing a Shared Bus for Cost-Efficient FPGA-Based Massively Parallel Architectures
in International Conference on Field-Programmable Technology (ICFPT'07), Japan, 2007
Schröder, J., Schimmler, M., Tischer, K., Schröder, H.:
IGOM - Iterative Generation of Position Frequency Matrices Maximising Signal to Noise Ratio in Finding Motifs in DNA Sequences
in HICOMB-Konferenz, Toronto, 2007
Güneysu, T., Paaar, C., Pelzl, J., Pfeiffer, G., Schimmler, M.:
Parallel Computing with Low-Cost FPGAs: A Framework for COPACOBANA
in ParaFPGA Symposium LNI, Jülich, 2007
Kumar, S., Paar, C., Pelzl, J., Pfeiffer, G., Schimmler, M.:
How to Break DES for EURO 8.980
in 2nd Workshop on Special-purpose Hardware for Attacking Cryptographic Systems (SHARCS'05), 2006
Kumar, S., Paar, C., Pelzl, J., Pfeiffer. G., Schimmler, M.:
A Cost-Optimized Special-Purpose Hardware for Code-Braking, poster summary
in IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), 2006,
pp. 311-312
Kumar, S., Pelzl, J., Pfeiffer, G., Schimmler, M.:
A Configuration Concept for a Massively Parallel FPGA Architecture
in International Conference on Computer Design (CDES'06), Las Vegas, 2006
Kumar, S., Paar, C., Pelzl, G., Pfeiffer, G., Schimmler, M.:
Breaking Ciphers with COPACOBANA -A Cost-Optimized Parallel Code Breaker, Cryptographic Hardware and Embedded Systems
in 8th International Workshop, Yokohama, Japan Proceedings. LNCS, Springer Verlag, 2006
Leibrich, J., Serbay, M., Baumgart, S., Rosenkranz, W., Schimmler, M.:
Receiver Sensitivity of Advanced Modulation Formats for 40 Gb/s DWDM Transmission with and without FEC
in European Conference on Optical Communication, pp. 1-2, 2006
Baumgart, S., Toledo, B., Spors, K., Schimmler, M.:
PLUG: An Agent Based Prototype Validation of CAD-Constructions
in The 2006 International Conference on Information and Knowledge Engineering, 2006
Pfeiffer, G., Kreft, H., Schimmler, M.:
Hardware Enhanced Biosequence Alignment
International Conference on Mathematics and Engineering Techniques
in Medicine and Biological Sciences (METMBS'05), Las Vegas, USA, 2005
Podschun, R., Bunimov, V., Noah, C., Pfeiffer, G., Schimmler, M.:
EGT - a tool for the identification of ESBL genotypes in Klebsiella
57. Jahrestagung der DGHM, Göttingen, 2005
Podschun, R., Bunimov, V., Noah, C., Pfeiffer, G., Schimmler, M.:
EGT - a tool for the identification of ESBL genotypes in Klebsiella
57. Jahrestagung der DGHM, Göttingen, 2005
Amanor, D. N., Bunimov, V., Paar, C., Pelzl, J., Schimmler, M.:
Efficient Hardware Architectures for Modular Multiplication on FPGA's
in 15th International Conference on Field Programmable Logic and Applications, pp. 539 - 54, 2005
Pfeiffer, G., Kreft, H., Schimmler, M.:
Hardware Enhanced Biosequence Alignment
in International Conference on Mathematics and Engineering Techniques in Medicine and Biological Sciences (METMBS'05), Las Vegas, 2005
Podschun, R., Bunimov, V., Noah, C., Pfeiffer, G., Schimmler, M.:
EGT - a tool for the identification of ESBL genotypes in Klebsiella
in 57. Jahrestag der DGHM, Göttingen, 2005
Schimmler, M. and Bunimov, V.:
Fast Modular Multiplication by Operand Changing.
In The International Conference on Information Technology ITCC pp. 518 - 524, 2004
Bunimov, V. and Schimmler, M.:
High Radix Modular Multiplication of Large Integers Optimised with Respect to Area and Timee,
In The 2004 International Conference on VLSI, 2004,
Schimmler, M., Bunimov, V.:
Reducing the Complexity of Modular Multiplication by Modification of one Operand, in: Nedjah, N., Mourelle, L.M. (eds.), Embedded Cryptographic Hardware: Design & Security, ISBN:1-59454-145-0,
2004
Schimmler, M., Bunimov, V.:
Two New Algorithms for Modular Multiplication, in: Nedjah, N., Mourelle, L.M. (eds.), Embedded Cryptographic Hardware: Methologies and Architectures, ISBN:1-59454-012-8, 2004
Bunimov, V. and Schimmler, M.:
Area and Time Efficient Modular Multiplication of Large Integers.
In The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'03), pp. 400-409, 2003
Bunimov, V., Schimmler, M. and Bziuk, W.:
Key Generation for Secure High Speed.
In The 2003 International Conference on Security and Management (SAM'03), 2003
Schimmler, M. and Bunimov, V.:
Reduction of Search Range for Prime Numbers.
In The 2003 International Conference on VLSI, 2003
Schimmler, M. and Bunimov, V.:
Efficient Parallel Multiplication Algorithm for Large Integers.
In Euro-Par. Springer-Verlag, 2003
Schimmler, M., Schmidt, B., Lang, H.-W., Heithecker, S.:
An Area-Efficient Bit-Serial Integer Multiplier,
VLSI'03, Las Vegas, NV, CSERA Press, 2003
Schimmler, M., Schmidt, B., Lang H.-W.:
Design of a Bit-Serial Floating-Point Unit for a Fine-Grained Parallel Processor Array, PDPTA'03, Las Vegas, NV, CSERA Press, 2003
Bunimov, V. and Schimmler, M. :
A Simple Algorithm For Time Optimal Modular Multiplication and Exponentiation.
In The Proceedings of the 15th IASTED International Conference PARALLEL AND DISTRIBUTED COMPUTING AND SYSTEMS, 2003
Bunimov, V., Schimmler, M. and Tolg, B.:
A Complexity-Effective Version of Montgomery's Algorithm.
In Workshop on Complexity Effective Designs (WCED02), 2002
Schimmler, M, Schmidt, B., Adi, W.:
Area Efficient Modular Arithmetic for Mobile Security,
ICWN'02, Las Vegas, 2002
Schmidt, B., Schröder, H., Schimmler, M.:
Massively Parallel Solutions for Molecular Sequence Analysis,
IEEE First Workshop on High Performance Computational Biology, Marriott Marina, Fort Lauderdale, Florida, 2002
Schmidt, B., Schröder, H., Schimmler, M.:
Protein Sequence Comparison on the Instruction Systolic Array,
PaCT'2001, LNCS 2127, Springer Verlag, pp 498-509, 2001
Schimmler, M:
Architectures and Algorithms for Multimedia Applications,
EuroPar'2000, LNCS 1900, Springer Verlag, p 1085, 2000
Schimmler, M., Schmidt, B.:
A Parallel Accelerator Architecture for Multimedia Video Compression,
EuroPar'99, LNCS 1685, Springer Verlag, pp 950-959, 1999
Schmidt, B., Schimmler, M., Schröder, H.:
Long Operand Arithmetic on Instruction Systolic Computer Architectures and ist Applications in Cryptography,
EuroPar'98, LNCS 1470, Springer Verlag, pp 916-922, 1998
Schmidt, B., Schimmler, M., Schröder, H.:
The Instruction Systolic Array in Tomographic Image Reconstruction Applications,
Proceedings PART'98, Adelaide, Australia, Springer Verlag, 1998
Schmidt, B., Schimmler, M., Schröder, H.:
Morphological Hough Transform on the Instruction Systolic Array,
In: Lengauer, C., Griebl, M., Gorlatch, S. (eds.), EuroPar'97, LNCS 1300,
Springer Verlag, pp 798-806, 1997
Schimmler, M.:
Der ISATEC Parallelrechner - eine PC-Zusatzkarte für rechenintensive Anwendungen in der Bildverarbeitung, Proc. IPK-Workshop Bildauswertung, 1996
Schimmler, M., Lang, H.-W.:
The Instruction Systolic Array in Image Processing Applications,
In: O. Loffeld, Vision Systems: Sensors, Sensorsystems, and Components, Proc. Europto 96, SPIE 2784, pp 136-144, 1996
Schimmler, M.:
A Bit-Serial Floating-Point Processor Below 10 mW,
Proc. ITG Fachtagung: Mikroelektronik für die Informationstechnik, Chemnitz, 1996
Schimmler, M.:
Konzept eines Chips mit 256 Prozessoren als Kernstück eines Instruction Systolic Arrays, Proc. Paraday, Stralsund, 1996
Schimmler, M., Riesemeier, H.:
Der ISATEC Parallelrechner beim Einsatz in der Röntgen und Computertomographie, Proc. BMBF Fachtagung HPCN, Jülich, 1995
Schimmler, M.:
Ein Gleitkommaprozessor auf 1mm2 Fläche,
Proc. 7. Eis-Workshop, Chemnitz, 1995
Schimmler, M.:
The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers,
Proc. High Performance Computing and Networking, München, 1994
Schimmler, M.:
Realisierung eines Instruction Systolic Array als Parallelrechner-Zusatzkarte für PCs,
Proc. Hochschul-Computer-Forum '93, Berlin, 1993
Schimmler, M.:
Instruction Systolic Arrays - Experiences With a First Implementation,
ISCA '92, Hamilton Island, Australia, 1992
Phieler, M., Schimmler, M., Schmeck, H.:
A Reconfigurable Instruction Systolic Array,
In: Dal Chin, M. Hohl, W. (eds): Fault Tolerant Computing Systems,
Informatik Fachberichte 283, Springer Verlag, pp 312-323, 1991
Schimmler, M., Schmeck, H.:
A Fault-Tolerant and High Speed Instruction Systolic Array,
Proc. International. Conference on VLSI '91, Edinburgh, Scottland, 1991
Schimmler, M., Schröder, H., Kunde, M., Maeder, A., Pham, B.:
A Linear Array of Rings for Local Operations in Image Processing,
Proc. International. Conference. on Automation, Robotics and Computer Vision, Singapore,
McGraw-Hill Book Co, pp 973-977, 1990
Schimmler, M., Beresford-Smith, B., Schröder, H.:
Fault Tolerance Through Reconfiguration in Binary Tree Embeddings,
Proc. IEEE International Workshop on Defect and Fault-Tolerance in VLSI Systems, Grenoble, pp 350-363, 1990
Schimmler, M., Starke, C.:
Fault-Tolerance for Comparison-Exchange-Sorters,
In: Reif, J.H. (ed): VLSI Algorithms and Architectures,
Lecture Notes in Computer Science 319, Springer Verlag, pp 444-445, 1988
Schimmler, M.:
Graphenalgorithmen auf dem Single Instruction Systolic Array,
Proc. PARS '88, Sprachen, Algorithmen und Architekturen für Parallelrechner,
Bad Honnef, pp 107-127, 1988
Schimmler, M., Schröder, H.:
Simple Systolic Method to Find all Bridges on an Undirected Graph,
In: v. Leeuwen (ed.): Graph Theoretic Concepts in Computer Science,
Lecture Notes in Compute Science 344, pp 262-267, 1988
Schimmler, M., Schröder, H.:
Simple Systolic Method to Find all Bridges on an Undirected Graph,
In: v. Leeuwen (ed.): Graph Theoretic Concepts in Computer Science,
Lecture Notes in Compute Science 344, pp 262-267, 1988
Kunde, M., Lang, H.W., Schimmler, M., Schmeck, H., Schröder, H.:
The Instruction Systolic Array and its Relation to other Models of Parallel Computers,
In: Feilmeier, M., Joubert, G., Schendel, U.(eds): Parallel Computing '85, pp 491-497, 1986
Lang, H.W., Schimmler, M., Schmeck, H., Schröder, H.:
A Method for Realistic Comparisons of Sorting Algorithms for VLSI,
Proceedings of the International Conference on Foundations of Data Organisation,
Kyoto, Japan, pp 236-240, 1985
Lang, H.W., Schimmler, H., Schröder, H.:
Pattern Matching in Binary Trees on a Mesh-Connected Processor Array,
In VLSI: Algorithms and Architectures, Bertolazzi and Luccio (eds.), North Holland, pp 113-124, 1984
Lang, H.W., Schimmler, M., Schmeck, H., Schröder, H.:
A Fast Sorting Algorithm for VLSI, Proc. 10th ICALP, Barcelona,
Lecture Notes in Computer Science, 154, pp 408-419, 1983
Referierte Veröffentlichungen auf nationalen Konferenzen
Koschnicke, S., Starke, Ch., Schimmler, M.:
Mobiler Aufgabenclient - Plattformunabhängige Mobilisierung von bestehender Software zur Disposition,
Tagung Software Engineering 2011 im 'Software Engineering Forum der Informatik-Transferinstitute, Karlsruhe
Koschnicke, S., Starke, Ch., Schimmler, M.:
KoSSE-Projekt - Universeller Aufgabenclient zur Unterstützung des technischen Betriebsmanagements
bei verteilter Datenhaltung,
Tagung Software Engineering 2010 im Software Engineering Forum der Informatik-Transferinstitute, Paderborn
Weitere externe Vorträge
Paulsen, N., Schatz, F., Schimmler, M.:
Hochperformantes hashbasiertes Short-Read-Alignment
Studierendentagung zu den Life Sciences in Kiel, Kiel, 2013
Schimmler, M.:
Auftragsforschung und Verbundprojekte zwischen Wissenschaft und Wirtschaft
Transferforum, Kiel, 2010
Schimmler, M.:
The Bus Concept of Systola 4096,
In: Brenner, K.-H., ElGlindy, H., Schmeck, H, Schröder, H. (eds.): Dynamically Reconfigurable Architectures, Dagstuhl-Seminar-Report 201, 1998
Schimmler, M.: Aggregate Operations - Key Elements of Efficient ISA Algorithms,
3rd MWA'98, Aachen, Germany, 1998
Schimmler, M.:
Erfahrungen beim Design des ISA-Prozesors,
Trinamic ASIC-Workshop, invited paper, Hamburg, 1997
Schimmler, M.:
Long Operand Arithmetik on the Instruction Systolic Array,
Proc. MWAA'97, Oberstdorf, 1997
Schimmler, M.:
Systola 16K - concept of a massivly parallel instruction systolic MIMD-System,
SWA'97, Logstor, Denmark, 1997
Schimmler, M.:
Das befehlssystolische Feld als Beispiel einer massiv parallelen Rechnerarchitektur, mehrfach;
z. B. wiss. Colloquium der Universität Jena, Universität Dresden, Universität Kiel, BAM, Berlin, FH Flensburg; FH Stralsund, 1995-1996
Schimmler, M.:
Ein Gleitkommaprozessor auf 1 mm2 Fläche,
mehrfach, z. B. wiss. Colloquium der Universität Karlsruhe, FH Aalen, 1995-1996
Schimmler, M.:
Leistungseffizienter Entwurf von Gleitkommaprozessoren;
mehrfach, z. B. FhG-IPK, Berlin, FH Kiel, 1995-1996
Schimmler, M.:
The Instruction Systolic Array Chip for Fast Computations on full Matrices,
Loughborough University of Technology, UK, 1995
Schimmler, M.:
Numerisch intensive Anwendungen Instruktionssystolischer Felder,
mehrfach, z.B. bei der SICAN GmbH, Hannover, der Bundesanstalt für Materialforschung, Berlin, dem IPK Fraunhofer Institut, Berlin, 1993-1994
Schimmler, M.:
Power-Efficient Integrated Circuit Design Using a True Single Phase Clocking Structure,
University of Aarhus, 1993
Schimmler, M.:
Full Custom Design eines fehlertoleranten Sortierchips,
Universität Hamburg, 1990
Schimmler, M.:
CMOS Design Experiences at Kiel University, University of Lyngby, 1990
Schimmler, M.:
The ISA-Processor as a 2 micron CMOS Design, University of Aarhus, 1990
Schimmler, M.:
An Instruction Systolic Array Chip for Fast Numerical Applications,
University of Odense, 1990
Schimmler, M.:
Pad Cells for Fast Off-Chip Communication, University of Lund, 1990
Schimmler, M.:
Design eines fehlertoleranten Shear-Sort-Chips, GMD, St. Augustin, 1989
Schimmler, M.:
Design, Simulation and Test of a Fault-Tolerant Shear-Sorter,
Daimi, University of Aarhus, 1989
Schimmler, M.:
Graphenalgorithmen auf dem Single Instruction Systolic Array,
Theorietag, Universität des Saarlandes, 1988
Schimmler, M.:
Fault Tolerant Sorting Networks,
Australian National University, Canberra, Austalia, 1988
Schimmler, M.:
Sorting on A Three Dimensional Processor Grid,
Daimi, University of Aarhus, 1985
Schimmler, M.:
Fast Sorters Based on Almost Sorted Rows, Daimi, University of Aarhus, 1985
Schimmler, M.:
Ein einfaches und schnelles paralleles Sortierverfahren für Gitterverbundene Prozessorfelder, Universität Hamburg, 1983
Patente
V. Bunimov, D. Wätjen, M. Schimmler: „Verfahren und Vorrichtung zum Verschlüsseln und Entschlüsseln von Daten“. Deutsches Patent DE0010148415.
V. Bunimov, D. Wätjen, M. Schimmler: "Method and device for the encryption and decryption of data". US Patent US2003091193.
V. Bunimov, D. Wätjen, M. Schimmler: "Method and apparatus for encrypting and decrypting data". EU Patent EP0001298834.
M. Schimmler, V. Bunimov: „Verfahren und integrierte Schaltung zur Durchführung einer Multiplikation modulo M. Patentanmeldung PCT/DE/01728.
